Buffer amplifiers providing high input and low output impedances and which operate over a wide frequency range are employed in a variety of signal processing circuits. A fundamental design of a bipolar transistor buffer amplifier, described by Knitter and Zuch in an article entitled "Unity Gain Buffer Amplifier is Ultrafast", Electronics, April 1978, pp. 124-124, is schematically shown in FIG. 1 as comprising a pair of push-pull stages coupled between an input terminal 20 and an output terminal 50. A first (push-pull) stage of the amplifier comprises an NPN input emitter follower transistor 10 the base 12 of which is coupled to input terminal 20, the collector 14 of which is coupled to a positive voltage supply rail 22 and the emitter 16 of which is coupled to a first current source 30 referenced to a negative voltage supply rail 24. The emitter 16 of input transistor 10 is coupled to the base 42 of an output PNP transistor 40, the collector 44 of which is coupled to the negative supply rail 24 and the emitter of which is coupled to output terminal 50.
A second push-pull stage comprises a PNP input emitter follower transistor 60 the base 62 of which is coupled to input terminal 20, the collector 64 of which is coupled to negative voltage supply rail 24 and the emitter 66 of which is coupled to a second current source 70 referenced to the positive voltage supply rail 22. The emitter 66 of input transistor 60 is coupled to the base 82 of an output NPN transistor 80, the collector 84 of which is coupled to the positive supply rail 22 and the emitter of which is coupled to output terminal 50.
The circuit configuration of FIG. 1 provides a high input impedance since input terminal 20 is coupled to base terminals of the input transistors 10 and 60, and provides a low output impedance since output terminal 50 is coupled to emitter terminals of the output transistors 40 and 80. The circuit's wide frequency response is achieved by coupling the signal flow path through emitter-follower transistor stages which are capable of operating at close to ft. Moreover, by selecting the magnitudes of current sources 30 and 70 to be sufficiently large to drive the parasitic base-to-collector capacitances of output transistors 40 and 80, the buffer is capable of achieving a high slew rate.
A major shortcoming of the circuit design of FIG. 1 is a d.c. input-output offset voltage through the base-emitter junctions of each push-pull stage. In the signal flow path through emitter follower input transistor 10 and output transistor 40, for example, there is a d.c. offset imparted by the series connection of base-emitter junction voltage Vbe of NPN transistor 10 and the base-emitter junction voltage Vbe of PNP transistor 40. How well this offset is minimized depends upon how well semiconductor processing parameters are able to match the NPN and PNP transistors. Since the respective input and output transistors are of opposite polarity types, the doping steps forming their base and emitter regions are carried out separately. Consequently, it can be expected that the devices will not match, so that a voltage offset (typically on the order of 20-40 millivolts) remains.
While d.c. offset may not be significant in all applications, it is critical at an input to a current feedback amplifier, as described in the U.S. Pat. to Nelson Nos. 4,358,739 and 4,502,020. In order for current feedback amplifiers, which offer certain advantages in terms of bandwidth, slew rate and settling time, to achieve the same degree of precision available in conventional voltage feedback operational amplifiers, it is necessary to substantially reduce the above-described d.c. voltage offset problem.
One proposal for reducing offset and also temperature drift in such a buffer amplifier design is shown in FIG. 2, which schematically represents a solution to the problem described in the U.S. Pat. to Saller et al No. 4,639,685. Specifically, respective complementary pairs of diode-connected transistors, which are sized to match the components of each push-pull stage, are coupled in the respective signal flow paths from input terminal 20 to output terminal 50. Thus, an additional diode-connected NPN transistor 110 is coupled between output terminal 50 and the emitter of PNP output transistor 40 in order to match out the Vbe of NPN input transistor 10, and an additional diode connected PNP transistor 160 is coupled between output terminal 50 and the emitter of NPN output transistor 80 in order to match out the Vbe of PNP input transistor 60. Similarly, an additional diode-connected NPN transistor 140 is coupled between the emitter of input transistor 10 and the base of output transistor 40 in order to match out the Vbe of PNP output transistor 40, and an additional diode-connected NPN transistor 180 is coupled between the emitter of PNP input transistor 60 and the base of output transistor 80 in order to match out the Vbe of NPN output transistor 80. In the circuitry configuration of FIG. 2, as long as the offset-complementing diode-connected transistors match their like polarity counterparts, offset and drift should be nulled. In practice, however, due to the inexactness of integrated circuit processing there can be expected to be some minor degree of residual mismatch between devices. Still, the residual offset and drift is typically an order of magnitude lower than what can be achieved by attempting to simply match opposite polarity devices.
Now although the circuit design of FIG. 2 substantially reduces the offset and drift problem of FIG. 1, it does not well serve the needs of a current feedback amplifier which requires that the output impedance of an associated input buffer amplifier stage be relatively low. By the addition of offset-compensating transistor diodes 110 and 160 in the output stages, the output impedance looking back into terminal 50 is effectively increased from that of FIG. 1. Moreover, the diode-connected transistors must have low parasitic collector resistance to avoid saturation and a drastic change in Vbe. This typically implies that the devices must be large area devices and therefore the matching transistors must also be large (in order for their emitter areas to match). Unfortunately, increasing the areas of the devices increases their parasitic capacitances thereby reducing signal processing speed. In addition, a finite early voltage will cause the transistor diodes to mismatch the other transistors, since they operate at different base-to-collector voltages.